In the prior art as depicted in FIG. 1, the low level audio signal (8) is injected into the input of a Pulse Width Modulator (1) having a signal which is referenced to ground. Said signal is then referenced to a negative voltage rail with the aid of Level Shifter (2). The negative rail referenced, pulse width modulated signal is typically fed to Driver (4) with the aid of High Side and Low Side Dead Zone (3) processing circuitry in order to avoid the simultaneous conduction of Output Switching Devices (6) and (7). Customarily a Feedback Resistor (9) is employed between Output (7) and the Pulse Width Modulator (1) in order to reduce non-linearities.
FIG. 2 depicts the typical circuitry within Driver (FIG. 1(4)). In the prior art depicted in FIG. 2, the Low and High Side Logic Level signals are fed to a pair of R/S Flip-Flops (1). The Signal Output of said R/S Flip-Flops is then fed to Level Shifter (2) in order to obtain a drive signal for the high current output Low Side Drive (6).
The High Side high current Driver (5) is driven by R/S Flip-Flop (4). The input to said R/S Flip-Flop (4) is also driven by another Level Shifter (3) to obtain a floating High Side signal. Pulse Generator (7) is introduced between Level Shifter (2) and Level Shifter (3) to ensure noise immunity and freedom from false triggering.
Level Shifter (3) is the most critical in high voltage, high frequency applications. The simultaneous presence of high voltage and high frequency requirements will introduce a thermal component in addition to that produced by the High Side Driver (5) and Low Side Driver (6). The two thermal components can be computed as CV.sup.2 F. Said two thermal components will limit the Power-Frequency product to approximately 125,000 WkHz.
The present invention exhibits a constant thermal component in respect to frequency, total freedom from false triggering, and a Power-Frequency product of 125,000 WkHz.
In its most common form, the functionality described above is implemented in a commercially available high density Integrated Circuit. FIG. 2 and the above description shows the large number of signal processing stages that said Pulse Width Modulated signal obtained at the output of the High Side and Low Side Dead Zone processing circuitry (FIG. 1 (3)) has to undergo.
The large number of said signal processing stages depicted in Driver (4) result in propagation delays in excess of the 100 nS range. For a Class D amplifier of relatively high power, say 200W into 8.OMEGA., a 100 kHz switching frequency can not be exceeded without impairing reliability. However, a 100 kHz switching frequency yields unacceptably high distortion in the higher registers of the audio band. A further limiting factor is the maximum .DELTA.v/.DELTA.t that can be obtained at the Output (7) without causing false triggering. A false triggering condition can lead to destruction of the Output Switching Devices (5) and (6).
The present invention overcomes the complexity and high cost of the prior solution by achieving the same functionality using discrete, inexpensive, "off-the-shelf" components while simultaneously increasing the flexibility of the resulting circuits, allowing the same topology to satisfy requirements from 50WRMS to over 100WRMS. Most importantly, the present invention allows higher switching speeds while improving reliability through superior .DELTA.v/.DELTA.t immunity. Typically, one may obtain a switching speed with no loss of reliability up to 5 MHz at 40V and 500 kHz at 200V.
Matching the propagation delays of the High Side and Low Side Drives is not a critical issue in the present invention as these are readily adjusted by appropriately choosing the component values of the Asymmetrical Delay Networks.